Qualcomm vs SiFive - Potential split in the ISA?

Recently Ian Cutress reported on layoffs at SiFive, however the more interesting story may be tension between Qualcomm and SiFive around the direction of RiscV.

Discussion in this thread on HN amoungst industry insiders indicated that Qualcomm is keen to deprecate variable length instructions and the C extention in order to simplify the implementation of high performance RiscV cores.

According to comments (I can find no link) SiFive has a strong preference for preserving the C extentions, presuably for code compression and performance reasons.

In this discussion on the RiscV.org mailing list Heinrich Schuchardt points out that if the C extentions are not mandatory, then when implementors/distros are making the decsion on what to support they will probably just default to the more compadible option of not supporting it and it will eventually die a slow death. Notably the tech-profiles mailing list has never seen so many posts in a single month before.

Other than the 32/64bit split this has the potential to be the most serious fragmentation of the RiscV ISA to date. We’ll be follwing this one closely.