Recently Ian Cutress reported on layoffs at SiFive, however the more interesting story may be tension between Qualcomm and SiFive around the direction of RiscV. Discussion in this thread on HN amoungst industry insiders indicated that Qualcomm is keen to deprecate variable length instructions and the C extention in order to simplify the implementation of high performance RiscV cores. According to comments (I can find no link) SiFive has a strong preference for preserving the C extentions, presuably for code compression and performance reasons.

Recently Christopher Barnatt on his YouTube channel ExplainingComputers has spent a week attempting to “live off the land” in a purely RiscV environment. In some respects it a great demo of how far things have come. A large portion what you would expect to work is in place, however some basic functionality such as the inability to use Yubikeys to authenticate via the browser (probably an issue with the libu2f-udev libraries) and the inability to run complex application with many dependancies such as Kdenlive/Blender.

The video and transcript below is the first exclusive for riscvnews.com - An interview with embedded chip designer Jeff Dionne. For many years Jeff has spearheaded development of the J-Core open source ISA. In our interview we try and look at where J-Core and RiscV differ and what opportunities both projects might have to learn from each other. If you’re using an old school audio player we also have a plain MP3 file of the interview.

As reported here a group of researchers have used AI modeling to re-invent a RISC-V chip from scratch with performance comparable to mid 90’s intel CPUs. One interesting point here, is that this work seems to be part of the push by China to foster more domestic development work focused on the RISCV ecosystem, as it is effectivley immune to sanctions. Assuming that this trend continues, we could expect to see a large number of AI generated CPUs conforming to the RISCV isa in the near future.

In an interview conducted by Jeff Geerling, Eben Upton discussed the possibility of migrating from ARM to RISCV for the next generation of Raspberry PI. Eben indicated that the main barrier was familiarity with ARM within the Raspberry PI foundation and the lack of maturity of tooling for RISCV. He did hint that if they were to move to RISCV it would be at the low end/microcontroller level first. Time link to the RISCV part of the interview here.

As reported here, developers in the xcp-ng community (the open source fork of Citrix Xen) have made progress in supporting Xen on Risc-V. KVM had support for RISCV merged in 2021, so it looks like VMware is the only major player missing out for now (which is slightly surprising given that they are an official RISCV member.

Pine64 the company behind the facinating (and currently flawed) PinePhone has taken a spin at creating a RISC-V based SBC (single board computer). Comments over at Hacker News seem to be pretty positive around the performance and specs (PCIe included!). You can pre-order one in the Pine64 store here.

ASUS has launched the first RISC-V small single board computer from a major vendor details here. At first blush it looks like a great option to play around with the RISC-V ecosystem, but there have been some discussions here on HN pointing out that they don’t implement the full spec - which may be a problem for people running Linux. Unfortunatley it does seem to be a “paper launch” with no pricing or information on vendors stocking the device.

VRoom! is an activley developed RISC-V implementation licenced under GPL3 (with commercial options). It is aiming for high performance (cloud server class), rather than embedded implementations. Although it does not seem to have the same level of backing as something like XiangShan, the development is much easier to follow for a western audience.